![]() The data they provide facilitates a greater understanding of chip performance and power activity and enables the SLM platform's analytics engines to drive more detailed and precise optimizations at each stage of the semiconductor lifecycle, from the early design phase, through in-field mission mode operation. The SLM process begins with the placement of the in-chip sensors and PVT monitors deep within the chip. The IP within the subsystem is a foundational element of Synopsys' Silicon Lifecycle Management (SLM) platform. In-chip sensing from Moortec, which is now a part of Synopsys, continues to be an essential element to achieve the highest levels of performance and reliability within today's advanced process technologies, underpinning optimization schemes, telemetry, and analytics. SoC designers targeting TSMC's most advanced process can utilize the deeply embedded PVT monitoring and sensing subsystem technology to assess key chip parameters during production as well as for measurement and analysis of real-time dynamic conditions during every stage of the device life cycle. The PVT monitoring and sensing subsystem IP has been added to the TSMC9000 Program, TSMC library and IP quality management program, offering customers a highly competitive performance advantage for a wide variety of target market applications including artificial intelligence (AI), data center, high-performance computing (HPC), consumer and 5G. Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of its DesignWare ® process, voltage and temperature (PVT) monitoring and sensing subsystem IP on TSMC's industry-leading N3 process technology. ![]() Designers benefit from a complete PVT subsystem providing real-time insights within the chip.Innovative, modular architecture offers new sensor technologies for advanced node devices.DesignWare PVT monitoring and sensing subsystem IP supports cutting-edge technologies targeting AI, data center, HPC, consumer and 5G markets.
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